A memory cell of EEPROM normally has a MISFET structure in which a charge accumulation layer and a control gate are stacked on a semiconductor substrate. The memory cell stores data in a nonvolatile manner based on a difference of the threshold voltage of a state in which the charge accumulation layer is filled with charges and the threshold voltage of a state in which charges are discharged. Charges are injected and discharged by a tunneling current via a tunnel dielectric film between the charge accumulation layer and a substrate channel. Among EEPROM, so-called NAND type EEPROM constituting a NAND cell unit by connecting a plurality of memory cells in series can be made denser because the number of selection transistors needed is smaller than in NOR type EEPROM. Also in a NOR type flash memory, data is erased by passing a tunneling current via a tunnel dielectric film between the charge accumulation layer and the substrate channel to suppress a short channel effect during an erase cycle. For example, to increase the number of memory cells erased in the unit time, data is erased simultaneously from a plurality of memory cells.
In a memory device, for example, a circuit that rearranges in series data read simultaneously from a plurality of the above NAND cell units to do input/output at high speed is provided. A MOS transistor for high-speed input/output of, for example, 200 Mbps (Mbps: Mega bit per second) to 400 Mbps is desired.
Incidentally, a MOS transistor having a gate in a laminated structure of, for example, a metal layer made of tungsten (W), a barrier metal layer made of tungsten nitride (WN), and a polysilicon layer from the upper layer side to reduce wire resistance of the gate has been known.
However, when a gate in such a laminated structure is formed, the resistance of the laminated structure between the barrier metal layer such as WN and the polysilicon layer is large and a problem in high-speed operation is caused. Such a problem is generally caused in a logic circuit such as a NAND circuit and NOR circuit. For example, the problem is also caused in an inverter circuit or a circuit used by connecting a plurality of logic circuits in series in a synchronous operation circuit used in a high-speed interface circuit.